1. Field of Invention
The present invention relates to a method of manufacturing a metallic interconnect. More particularly, the present invention relates to a method of manufacturing a copper interconnect.
2. Description of Related Art
As the level of integration of integrated circuits increases, the number of metallic interconnects necessary for connecting all the devices within a silicon chip also increases. Consequently, designs having two or more metallic layers are becoming standard. In the manufacturing of deep submicron integrated circuits, reliable metallic interconnects are difficult to produce due to the high level of integration. Furthermore, interconnects that are formed inside ultra-high level integrated (ULSI) circuits must have sufficiently good electrical connectivity despite having a small junction area. At present, aluminum is frequently used as the base material for fabricating metallic interconnects. However, as the level of integration continues to increase, copper is increasingly being used. Copper has many advantages over aluminum including a lower resistivity, a higher resistance to electromigration, and a higher melting point (copper's melting point is 1060.degree. C. compared with aluminum whose melting point is only 660.degree. C.). In addition, when copper circuits are formed with a silicon chip, operating efficiency can increase up to twice that of the same circuits using aluminum. A copper conductive wire not only can lower RC delay in a circuit, but is also capable of reducing the amount of static electricity stored between conductive wires. Hence, copper is now an important material for forming metallic interconnects.
There are two conventional methods of fabricating metallic interconnects. In the first method, a metallic layer is formed over a substrate, and then a patterned photoresist layer is formed over the metallic layer. Thereafter, using the patterned photoresist layer as a mask, the metallic layer is etched to form metallic lines. Finally, an inter-metal dielectric layer is deposited over the metallic lines. In applying the first method of forming metallic interconnects, the surface of the metallic layer can easily reflect unwanted light back, which leads to errors in the photolithographic operation. Moreover, due to the tougher material properties of metal, etching a metallic layer is much more difficult than etching a dielectric layer.
The second method of fabricating metallic interconnects is commonly known as a damascene process. After a metallic plug is formed in a substrate, a dielectric layer is deposited over the metallic plug and the substrate. The thickness of the dielectric layer should be roughly equal to the intended thickness of the metallic wires. Next, a patterned photoresist layer is formed over the dielectric layer, and then the dielectric layer is etched to form a trench that exposes the metallic plug. Finally, metallic material is deposited into the trench, thereby forming an electrical connection with the plug.
Another method of fabricating metallic interconnects whose processing steps are very similar to that of the damascene process is known as a dual damascene process. The main difference between them is that the damascene process begins after a metallic plug has already been formed in the substrate. In the dual damascene process, first a via opening and a trench pattern are formed in a dielectric layer. Then, metallic material is deposited to fill the via opening and the trench at the same time, thereby forming the interconnects and inter-layer plug connection in a single operation.
FIG. 1 shows a cross-section of a copper interconnect fabricated using a conventional dual damascene process. In FIG. 1, label 100 represents a semiconductor substrate, label 102 represents a dielectric layer, label 104 represents a copper layer, label 106 represents inter-metal dielectric layer, label 108 represents a via opening, label 110 represents a trench opening, and label 112 represents a copper oxide layer. Before carrying out the dual damascene process, some device structures (not shown) such as transistors have already been formed over the semiconductor substrate 100. Then, a dielectric layer 102 is formed above the substrate 100. Embedded within the dielectric layer 102 is a copper layer 104, which acts as a conductive wire. Above the dielectric layer 102, there is an inter-layer dielectric layer 106 having a via opening 108 and a trench opening 110 that expose the copper layer 104. Because copper can be oxidized easily when exposed to air, a copper oxide layer 112 is also formed over the exposed copper layer 104 after the etching operation. Copper oxide is electrically non-conductive. Therefore, if metallic material is directly deposited over the oxide layer following a normal procedure, the via will have a very high resistance, which is undesirable. Consequently, the copper oxide layer 112 should be removed before a barrier layer (not shown) is coated over the interior of the via opening 108, the trench opening 110 and the copper layer 104. Finally, copper is deposited into the openings 108 and 110 to form a copper interconnect and a via plug (not shown).
FIG. 2 is a diagram showing a conventional method that uses radio frequency (RF) argon (Ar) to remove a copper oxide layer above a copper layer. In FIG. 2, radio frequency argon atoms 114 are used to bombard the bottom part of the via opening, thereby removing copper oxide from the surface. However, while bombarding with atomic argon, some copper atoms 104' are struck out from the copper layer 104 and penetrate the sidewalls of the via opening 108. Finally, the straying copper atoms 104' are trapped inside the inter-metal dielectric layer 106.
Since the inter-metal dielectric layer 106 is not covered by a barrier layer, the copper atoms 104' will diffuse into the interior of the inter-metal dielectric layer 106 after performance of some related thermal operations. Copper has a high diffusion rate inside the inter-metal dielectric layer 106, and hence can easily move into the device area of a substrate. Therefore, the devices may be contaminated and quality of the resulting device is inferior. Furthermore, the diffusion of copper also leads to unwanted electrical connection between two isolated conductive structures. Thus, efficiency of the devices is lowered and reliability of the metallic interconnects may become a problem.
In addition, before the deposition of metal into the via opening and trench opening, a barrier layer that can prevent atoms diffusing from a conductive layer into the inter-metal dielectric layer is normally formed first. Hence, a barrier layer is inserted between the copper layer and the subsequently deposited metallic layer. However, with the presence of a barrier layer, resistivity of the via plug inside the via opening increases.
In light of the foregoing, there is a need to provide a better method of fabricating copper interconnects.